Static Random Access Memory (SRAM) is a common type of its non-volatility, low power dissipation, and applicability to high-speed operations.
One example of an SRAM memory cell is illustrated in FIG. 5. It is the so-called eight-transistor (8T) SRAM cell, where the eight transistors in a cell are labeled M1 through M8. In FIG. 5, the write word-line is labeled WWL, the write bit-line and its complement are labeled WBL and WBL#, respectively, the read word-line is labeled RWL, and the read bit-line is labeled RBL.
Operation of the SRAM cell illustrated in FIG. 5 is well known and need not be described in detail; however, it is pedagogically useful to discuss some features of the cell so as to motivate the embodiments described later.
As is well known, transistors M1 through M4 comprised two cross coupled inverters to store the state of the memory cell. Pass transistors M5 and M6 allow the state of the memory cell to be changed during a write operation, and pass transistor M7 and pull-down transistor M8 allow the state of the memory cell to be sensed during a read operation. Before a read operation is performed, the read bit-line RBL is pre-charged to the supply voltage Vdd, and when the supply voltage is provided to the read word-line RWL to perform a read, the read bit-line RBL is either pulled down to the substrate voltage Vss or kept at the supply voltage Vdd, depending upon the state of the memory cell.
A so-called weak bit is a memory cell that has relatively low current capacity compared to an ideal memory cell. This degradation is usually due to process-voltage-temperature (PVT) device variations. The cell-read-current of a weak bit may affect and degrade the performance of an SRAM cache memory, for example. Also, a weak bit has higher voltage sensitivity due to a higher threshold voltage, which may result in performance degradation more severe than that due to supply voltage noise.
Process variation also limits the minimum write voltage (Vmin) of an 8T cell, and this sets the overall minimum operation voltage for single rail processor circuits that employ SRAM cache. Mobile processors may be required to perform to an aggressive power specification; therefore, lowering the 8T cell Vmin is important.